1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits, such as CPUs including highly scaled transistor elements, and compensation techniques for enhancing product performance.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and increase of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are based on silicon, due to substantially unlimited availability, the well-understood characteristics of silicon and related materials and processes and the technological experience gathered during the last 50 years. Therefore, silicon will likely remain the material of choice for future circuit generations designed for mass products. One reason for the dominant importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has continuously been decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current while also requiring enhanced capacitive coupling of the gate electrode to the channel region. Thus, the thickness of the silicon dioxide layer has to be correspondingly decreased to provide the required capacitance between the gate and the channel region. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, high speed transistor elements having an extremely short channel may preferably be used for high speed applications, whereas transistor elements with a longer channel may be used for less critical applications, such as storage transistor elements, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range or 1-2 nm that may represent limitations for performance-driven circuits. That is, product reliability and lifetime are strongly correlated with short channel effects, i.e., impact ionization and hot carrier injection (HCI) in combination with gate dielectric leakage.
Consequently, significant efforts are made in improving manufacturing technologies in an attempt to achieve a high yield of products meeting predetermined specifications in terms of performance, reliability and lifetime. For example, any improvements with respect to power consumption, which may be associated with the introduction of new technologies, may translate into improved performance only if the power envelope, that is, the area defined by the allowable maximum supply voltage and the maximum thermal power, remains substantially unchanged. Similarly, further device scaling may be correlated with increased operating speed of the product under consideration, while nevertheless increased power consumption may exceed the allowable design power, thereby not taking significant advantage of the reduced dimensions of the components. Hence, also in this case, a product manufactured by highly sophisticated technologies may still have to be considered as a product of the same specification category irrespective of the advanced manufacturing technologies, which may possibly come along with increased production costs. Furthermore, in aggressively scaled semiconductor technology, despite any measures taken to guarantee lifetime and reliability of these products, a generally increased degradation of product performance over operating time may be observed, which may have to be taken into consideration when grouping the various products into specific categories, since the respective product has to meet the specifications over the entire lifetime of the product. For example, in advanced microprocessors, this kind of performance degradation manifests itself in a strong degradation of the maximum operating frequency with increasing operating time.
In order to ensure the desired product performance over the entire product lifetime, for instance ten years for microprocessor products, appropriately selected specifications have to be used in which corresponding safety margins or “guard bands” are included to guarantee that a product having characteristics corresponding to a lower limit of the performance specification may nevertheless stay within the specified range during the entire lifetime. This means that, for instance, microprocessors having a specific initial maximum operating frequency may have to be considered as products of lower speed grade, since the degradation in performance over the entire lifetime may finally result in a reduced maximum operating speed that would no longer be within a category corresponding to a higher speed grade.
FIG. 1a schematically illustrates the temporal progression of product performance, for instance in the form of the maximum operating frequency Fmax of microprocessor products, over the lifetime, such as 10 years, wherein an initial state of the product, indicated as I, may correspond to a certain maximum operating frequency, which decreases or degrades over time so as to arrive at a significantly lower state F representing the performance at the guaranteed lifetime of the product. It should be appreciated that the curve connecting the states I and F is a simplified presentation which, however, qualitatively illustrates the performance degradation of sophisticated integrated circuits.
FIG. 1b schematically illustrates a power envelope representation in which the thermal design power of an integrated circuit is plotted against a performance parameter, such as the maximum operating frequency Fmax of microprocessors, wherein an upper limit for the thermal design power is indicated by TPL. Furthermore, an area A is illustrated in which products are included having a certain maximum operating speed or frequency as determined after fabrication of the devices while also respecting the upper limit TPL of the thermal design power. Furthermore, for the area A, a lower frequency limit is determined that indicates the lowest allowable Fmax so as to specify an actual product speed, indicated as “product speed” for a product segment A. That is, the product speed represents the required performance of the product in actual applications, which is, however, significantly lower than the lower Fmax limit of the area A due to the time dependent performance degradation. However, as explained above with reference to FIG. 1a, the product degradation over time may conventionally be taken into consideration by a corresponding “performance guard band.” For example, a product having the maximum operating frequency I after fabrication may have the status F after the lifetime, wherein the status F has to be above the product speed, thereby requiring a moderately wide guard band. Consequently, any products having an initial maximum frequency which is located within the guard band may have to be grouped into a lower product speed segment, thereby reducing the profitability of the entire manufacturing process, as high speed products may typically be sold at higher prices.
As a consequence, reducing the guard band as much as possible may be highly desirable in view of increasing the profitability of the corresponding manufacturing process. In order to increase the number of parts fulfilling high performance requirements, an improvement in technology, for instance the advance to a next technology generation or an improvement in overall product design, may be required but may be associated with significant process modifications resulting in increased research and engineering efforts, thereby contributing to increased production costs.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.